From: Adam Krolnik (adamk@cyrix.com)
Date: Mon Apr 06 1998 - 21:04:28 PDT
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE55
Errata Name (Description): Implicit net type definition
Section: 3.5, page 16
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The first paragraph states that only signals connected to a
primitive, UDP or module instance assume an implicit net declaration. The
third paragraph says the assumed data type is scalar. Verilog-XL and other
simulators also assume an implicit net data type for the left-hand side of
continuous assignments, and will assume a vector size if the net is connected
to a vectored port. The submitter believes there may be other circumstances
where an implicit vector net is assumed. The exact rules for assuming
implicit net types needs to be defined.
-----------------------------------------------------------------------------
Here is an example that neither XL or VCS will compile because continuous
assignments do not implicitly declare a net. If lines 3 and 10 (the references
to 'b') are removed, then both simulators will report a width mismatch on
the connection of 'c' to port 'C' - indicating that implicit declaration
of nets results in a scalar net.
Recommendation:
Current text correctly defines when implicit net declaration occurrs and
the default definition of a net.
module test;
assign b = 4'hf;
ins in (.a(1'b1), .b(1'b0), .C(c));
reg a;
initial begin
$display("Result is %0b.", b);
end
endmodule
module ins(a,b,C);
input a,b;
output [1:0] C;
wire [1:0] C = {a,b};
endmodule
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM.
Richardson Tx. 75085
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