From: ???@???
Date: Thu Jun 24 1999 - 11:01:47 PDT
Good afternoon Anders:
I would like to extend this enhancement:
This is one specific instance of a more general specification problem:
"There is no restriction of one declaration of a symbol for a given type."
Compare the errors reported by different simulators for this example
program (at end of mail.)
XL reports 13 errors (all redefinitions of a previous symbol.)
VCS only reports 7 errors (t1, f and t.) Not even a redefinition
of the type of t2 or t1 is reported!
I propose the following additional wording (note I attempted to list
each section defining a type):
Add this sentence to the end of the first paragraph in section
3.2.1 "Net declarations" and 3.2.2 "Register declarations" and before
last sentence of section 3.11 "Paramters".
"It is illegal to redeclare a name already declared by a net, parameter or
register declaration. "
Replace the last sentence of 3.12 "Name spaces" with
"Once a name is used to define a module, macromodule or primitive, the name
shall not be used again to declare another module, macromodule or
primitive."
Add to the third paragraph (sentence) that reads, "There are four
local name spaces..."
"Once a name is defined within one of the four name spaces, it shall
not be defined again with the same type or another type."
Add to the end of the second paragraph in section 12.4 "Port declarations"
"Once a name is defined in a port declaration it shall not be defined again
with the same type or another type."
Add to the end of the last paragraph of section 12.2.2.2 "Parameter value
assignment by name"
"Once a parameter is assigned a value, there shall not be another assignment
to this parameter name."
Add to the end of the last paragraph of section 12.3.1 "Port definition"
"Once a port has been defined, there shall not be another port definition
with this same name."
[NOTE: This seems to be supported - and produces not even a warning.
Why is this so?]
Add to the end of the first paragraph of section 12.3.4 "Connection module
ports by name"
"Once a port is connected by name, there shall not be another named
port connection for this port."
-----------------------------------------------------------------------
% cat /tmp/f.v
module test(a, a);
input a;
inout a;
parameter t3 = 1;
reg t3;
wire t3;
tri1 t3;
// Declare a register, wire, function, task multiple times. Which
// are errors?
reg t1;
reg t1;
wire t2;
wire t2;
tri1 t2; //Redefine type too - is this an error?
wire t1; //Redefine reg type!
function f;
input d;
reg f;
begin
end
endfunction
function f;
input d;
reg f;
begin
end
endfunction
task t;
input d;
begin
end
endtask
task t;
input d;
begin
end
endtask
endmodule
<p><p> Adam Krolnik
Verification Engineer
Cyrix - NSC.
Richardson TX. 75085
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