From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Tue Jul 06 1999 - 15:35:10 PDT
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Team,
<p>Could someone please review the BE90 errata regarding bit lengths resulting
from
<br>expressions and write a proposal. We could discuss it a our next conference
call
<br>but I'd rather spend that time on larger issues.
<p>Thanks,
<p>
Anders
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<H2> BE90 - Bit lengths resulting from expressions </H2>
<TABLE BORDER COLS=2 WIDTH="75%" >
<TR><TD>
Section: </TD><TD> TBD
</TD></TR><TR><TD>
Date Submitted: </TD><TD> 990607
</TD></TR><TR><TD>
Requestor: </TD><TD> Tom Fitzpatrick
</TD></TR><TR><TD>
Status: </TD><TD> Submitted
</TD></TR><TR><TD>
Analyzed by: </TD><TD> TBD
</TD></TR>
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<H3> Details </H3>
The width of a multiplication in the de facto standard Verilog-XL is the
same as the other binary operators: max(L(i),L(j)). This should be fixed
in the spec.
Note that multiplication without losing any overflow bits is still possible
simply by assigning the result to something wide enough to hold it.
Even if it were decided that XL is wrong and the spec is right, there is
still a problem with the width for the power operator. Consider the
innocuous looking case of 2**2. The value of this expression would
require 8 times more memory than the processor can even address (e.g.
32 Gigabytes for a machine with 32 bit integers). The literal '2' is
32 bits wide, and with the exponentiation in the width, this blows up
into a huge width for the result.
<PRE>
---------------
Tom Fitzpatrick
Senior Technical Marketing Manager Cadence Design Systems, Inc.
RTL Verification Flow/Product Engineering 270 Billerica Rd.
Design and Verification R&D Chelmsford, MA 01824
x6438 (978)446-6438
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