From: Michael McNamara (mac@verisity.com)
Date: Sat Apr 08 2000 - 15:32:59 PDT
John W. Curtis writes:
> I just read an article in the EE Times from a week ago or so. From what I
> read it would appear that two years of comments from our organization to the
> likes of Synopsys, Mentor and Cadence have failed to reach anyone who could
> affect the language, and the latest revision, Verilog 2000, is still missing
> some rather obvious features.
>
> Although I presume that the items below have missed the boat for this pass
> and have no hope of making it into the language for at least another four
> years, I would like to offer them for placement on the list for future
> committee discussion.
>
> 1. Verilog needs a preprocessor. #include, #define and #pragma should all be
> implemented. There is also a need for the #ifdef, #else, and #endif
> constructs, even though these can be accomplished by other means.
In Verilog 1364-1995 there was `include, as well as `define, `ifdef,
`else and `endif.
In Verilog 1364-2000 we added `ifndef. We thought hard about `pragma,
but could not come to consensus, and remain with the universal
practice of // synopsys translate_off in place.
Is this OK? Do you have a particular affinity for #ifdef as opposed to
`ifdef? Or perhaps the tool suite you are using does not support
`ifdef et al?
The reason # was not used was because we were already using it for delays.
> 2. Verilog needs more hooks for synthesis. In the FPGA world, were our
> organization spends most of its time, all place and route engines work on
> annotated netlists. Verilog needs a way to place annotations on nets. The
> #pragma construct from C would work.
Verilog 1364-2000 added annotations for every construct. The syntax
is (* name=value [,name=value]* *)
> 3. The superfluous distinction between "=" and "<=" should be
> dropped.
Interesting comment. Would you then make every assignment blocking? Or
would you make everything non blocking? What would you do with
existing libraries?
> The "ASSIGN" keyword should be dropped.
I personally would agree here; albeit, not enough is gained, assuming
you retain 'force' and 'release'
> The curly braces from C should be allowed as an alternative to
> "BEGIN" and "END. Where possible, all Verilog syntax should be
> conformed to the corresponding elements of ANSI C.
I also don't like (never did) the BEGIN and END reminders of Verilog's
root in Pascal. However, one does run into an ambiguity between a
left hand side concatenate, and a new block.
> 4. Global varibles and signals should be allowed.
All variables in verilog are global, and can be referenced from any
point in the design hierarchy. It is VHDL that has the concept of
signals and variables, and the distinct lack of global access to any.
>
> Jack Curtis
> Fortel DTV
> 404-885-9555
>
>
>
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