From: Shalom Bresticker (r50386@email.sps.mot.com)
Date: Sun Sep 24 2000 - 01:08:18 PDT
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Section 3.2.1 starts, "The net data types shall represent physical connections
between structural entities, such as gates."
<p>The word "shall" is not appropriate here. It is true that this
is the common use of net types, but it is not the only use.
<p>Similarly, 3.2.2 starts, "A variable is an abstraction of a data
storage element."
<p>Again, an absolute statement which is not the only possibility.
<p>The statements often cause confusion among Verilog users, as seen below,
and especially when learning Verilog for the first time.
<p>Much better would be to write "may" or "may be" instead of "shall" or
"is".
<p>And statements should be added to clarify that the LRM does not
restrict the usage of data types, only defines their behavior.
<p>A similar confusion occurs between logical and bit-wise operators, though
this time it is not the fault of the standard. Bit-wise operations on 1-bit
operands are exactly the same as logical operations, yet I have often
heard the claim that only logical operators should be used on signals,
because "logical operators are intented for signals and bit-wise operators
are not," although there is absolutely no support for such a statement
anywhere.
<p>Shalom
<br>
<p>-------- Original Message --------
<table BORDER=0 CELLSPACING=0 CELLPADDING=0 >
<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>From: </th>
<td>"Shalom Bresticker (r50386)" <r50386@email.sps.mot.com></td>
</tr>
<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>Subject: </th>
<td>Re: Fwd: Verilog Races in Combinatorial Logic</td>
</tr>
<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>To: </th>
<td>Jskud@cypress.com</td>
</tr>
<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>CC: </th>
<td>sjmeyer@pragmatic-c.com, stuart@sutherland-hdl.com, sharp@cadence.com,
btf@boyd.com</td>
</tr>
</table>
<p>"Joseph P. Skudlarek" wrote:
<blockquote TYPE=CITE>Bottom line: The meaning of a Verilog description
is a real issue; the
<br>current overly-inclusive specification does not ensure current practice
<br>behaves as intended, nor does it support a useful modeling style.
If
<br>the standard is to meet the goals of being clear, complete, and correct,
<br>then these issues must be addressed.</blockquote>
Agreed.
<br>See comments below.
<blockquote TYPE=CITE>
<p>Given the importance (after all, simulation semantics are essential
to
<br>using Verilog) and the uncertainty (experts disagree on what's specified
<br>-- how can we expect the user community to embrace the standard?),
I
<br>agree that it's worth delaying the standard to resolve these issues.
<p>Specific comments follow. /Jskud
<p>------------------------------------------------------------------------
<br>Joseph P. SKUDLAREK
Jskud@cypress.com direct 503/526-1874
<br>Data Communications Division 9125 SW Gemini Dr #200
FAX 503/626-6688
<br>Cypress Semiconductor Corp Beaverton Oregon 97008
www.cypress.com
<br>------------------------------------------------------------------------
<p>You're absolutely right, Shalom, the example you provide
<p>> initial begin
<br>> for (i = 0; i < 100; i = i + 1) array1[i] = i ; //
initialize array1
<br>>
<br>> initial begin
<br>> for (i = 0; i < 527; i = i + 1) array2[i] = 2*i +
4 ; // initialize array2
<p>should be totally deterministic regarding the resulting values in array1
<br>and array2 after initialization. The essential point which the
standard
<br>does not address is whether or not i is a "shared variable".
<p>To support the natural interpretation, i must not be a shared variable
<br>if i is declared integer. But if i is declared reg, there is
a problem,
<br>since given the scoping rules, i is a shared register, making it a
<br>shared variable, making it possible for the loops to interact.
<p>I make the distinction between reg and integer, because (1364-1995)
<p> A register is an abstraction
of a data storage element. (p. 3-2)
<p> An integer is a general purpose
register used for manipulating
<br> quantities that are not
regarded as hardware
<br> registers. (p. 3-12)
<p>but this may be splitting hairs that don't really exist (yet).
<p>/Jskud</blockquote>
Yes, that is splitting hairs that do not exist.
<p>1364-2000 (2001?) says in place of the first sentence:
<p>"A <i>variable</i> is an abstraction of a data storage element."
<p>And section 3.9 says about regs and integers:
<p>"In addition to modeling hardware, there are many other uses for variables
in an HDL model.
<br>Although reg variables can be used for general purposes such as counting
the number of times a particular net changes value, the integer and time
variable types are provided for convenience and to make the description
more self-documenting."
<p>Shalom
<br>
<br>
<pre>--
************************************************************************
Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
<a href="http://www.motorola-semi.co.il/">http://www.motorola-semi.co.il/
</a>************************************************************************</pre>
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