From: Michael McNamara (mac@verisity.com)
Date: Fri Oct 06 2000 - 11:20:02 PDT
Adam Krolnik writes:
>
>
> Anders wrote:
>
> --------------------------------------------------------------------
> Comment 6: page 41
>
> Attributes are not mentioned in the discussion of name spaces
>
> PROPOSAL: Add attributes to module name space. Add attributes to
> the list in the second paragraph from the bottom on
> page 41.
> -----------------------------------------------------------------
>
> I don't think that the question of whether attributes are part
> of a name space is relevant. You can and should be able to have
> the same attribute name on several elements of the language.
> You should be able to list an attribute several times on a
> language element. There should be no restriction of attribute
> names (unless you exclude Verilog keywords for simpler tokenizing.)
>
> Why should we say, 'attribute names belong to the same space as
> names inside a module'. E.g. this should be okay.
>
> module foo;
>
> (* a=1 *)
> input a;
>
> task my_task;
> ...
> endtask
>
> (* my_task *) function f (a, b, c);
>
> I know most attributes are going to be something like,
>
> synopsys_rtl_no_translate
> synthesis_use_cla
> surefire_lint_off
> avanti_placehere
> xyxgrgl_dontcoredump
>
> But I might want
>
> testname - name tests that break my design - multiple places
> here.
> dv_corner
> counter
>
> And not want to tell users, 'please don't use these names in your
> code...'
>
>
> Counter proposal:
> Add a note to section 3.12 indicating that attribute names are not
> part of any name space and are not themselves within one - each
> use of an attribute_spec is independent of the others.
>
Second.
--
//' Michael McNamara <mac@verisity.com>
_ // Sr VP Technology 650-934-6888
\ // Verisity Design 650-934-6801 FAX
\// <http://www.verisity.com> 408-202-1137 Cell
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