Re: JohnW Comment 66 - 70 Ballot LRM Feedback

From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Fri Oct 27 2000 - 03:05:17 PDT


For #68, the following sentence in your proposal is unclear: "Such usages shall be
substituted after the original macro is substituted, not when it is defined."

<p>

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On Thu, 26 Oct 2000, Steven Sharp wrote:

> > JohnW-Comment #66: p. 340, Section 18.2.3.2, $date, should default to the > > yyyy MM dd > > hh:mm:ss format, which makes sorting things by date much easier. > > NO CHANGE > > This might be useful, but would not be backward compatible with the > existing implementations and all the VCD files already out there. > > > JohnW-Comment #67: p. 342, Section 18.2.3.8, $var, seems to have a typo in > > the final > > example: Shouldn't the format be, "integer 32 addr[31:0]"? The unmatched > > parenthesis here and elsewhere makes me uneasy. > > NO CHANGE > > There is some justification for this. However, an integer always has a > range of [width-1:0], so putting this information into the VCD file would > be redundant and a waste of file space. > > The parenthesis is part of the identifier_code. It is simply a printable > ASCII character in this context, and is not required to match anything. > Relax :-). > > > JohnW-Comment #68: p. 360, Section 19.3.1, ' define, I suggest some text or > > a Note > > explaining whether recursion is allowed in macroes, and whether macro > > references > > are allowed in macro definitions. For example, is this legal: > > 'define nand reg nand['high_bit:'low_bit] > > CLARIFICATION > > Add new text or a note stating: > > The macro text can contain usages of other text macros. Such usages > shall be substituted after the original macro is substituted, not when > it is defined. It shall be an error for a macro to expand directly > or indirectly to text containing another usage of itself (a recursive > macro). > > > JohnW-Comment #69: p. 360, Section 19.3.2, ' undef, the final text should > > be expanded to > > read, "A 'undef'ed text macro has no value and no name; any subsequent > > appearance of the 'name shall be replaced by the compiler by one > > whitespace" (or, > > maybe, be removed?) > > CLARIFICATION > > Neither suggested alternative is the correct behavior. Using an undefined > macro is an error in Verilog-XL and NC-Verilog, whether it was never defined > or was defined and then undefined. > > Here is another suggested alternative: > > An undefined text macro has no value, just as if it had never been defined. > > > JohnW-Comment #70: p. 364, Section 19.6, ' resetall, the first line of text > > should read, ". . . > > all compiler directives except 'line are set to the default . . .". Also, > > where are the > > default values listed? They should be in a table or Annex referenced here. > > UNSURE > > I agree that `resetall should not reset `line, as suggested here. The > defaults are stated or implied elsewhere in the section, but may not be > clear to everyone. The default for `timescale does not appear to be > stated. Verilog-XL uses 1s/1s, which is generic but not useful for real > hardware. NC-Verilog uses 1ns/1ns. Other defaults appear to be > `endcelldefine, `default_nettype wire, and `nounconnected_drive. >



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