shift-reduce conflict in verilog-2000 grammar

From: Steven Sharp (sharp@cadence.com)
Date: Wed Nov 01 2000 - 13:04:26 PST

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>From pgraham Wed Nov 1 15:53 EST 2000
Date: Wed, 1 Nov 2000 12:53:00 -0800 (PST)
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From: Paul Graham <pgraham>
To: sharp
Subject: shift-reduce conflict in verilog-2000 grammar

Steve,

This may not be of interest to the NC group, but the Verilog-2000 grammar
for ANSI-style ports requires two tokens of lookahead:

    module m(input a, b);
                    ^
    module m(input a, input b);
                    ^

Upon encountering the ',', a yacc parser cannot tell if the list of names
associated with the 'input' keyword will continue, or if another keyword
will occur.

I suspect this is why ANSI C allows:

    int f(a, b, c)
    int a, b, c;

but disallows

    int f(int a, b, c)

instead requiring

    int f(int a, int b, int c)

In VHDL it's not a problem because of all the additional tokens in a
declaration. In particular, identifiers in a list are separated by ',', but
groups of declarations are separated by ';':

    port(a, b : in bit; c : in bit);

I understand that NC uses a recursive-descent parser, so you probably won't
be affected by this peculiarity of the grammar. But I'm stuck with a yacc
parser, and perhaps other Verilog tool developers are as well.

Two possible ways to fix this yacc conflict:

    1) disallow more than one identifier per i/o keyword (like ANSI C)
    2) separate identifier list from following keyword with ';'

Do you suppose you could bring this to the attention of the Verilog-2000
committee?

Paul
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