From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Wed Aug 01 2001 - 08:30:00 PDT
The following reply was made to PR errata/5; it has been noted by GNATS.
From: Stuart Sutherland <stuart@sutherland-hdl.com>
To: btf-bugs@boyd.com, btf@boyd.com
Cc: btf@boyd.com
Subject: Re: errata/5: Bad description of implicit nets created from
continuous assignments
Date: Wed, 01 Aug 2001 08:27:21 -0700
My "Verilog-2000" presentation become the de facto standard? I HOPE NOT!
Just to set the record straight, my "Verilog-2000" presentation was created
for HDLCon 2000. I had to submit the paper and examples in January 2000,
several weeks before the ballot draft for the 1364 LRM was complete. A
couple of specifications changed between when I wrote the paper and the
actual ballot draft, such as attributes. As a result of the balloting,
some more things changed, such as the rules for constant functions. And,
alas, the ballot review process took so long that the standard became
"Verilog-2001" instead of "Verilog-2000".
In regards to implicit nets on the LHS of continuous assignments, my text
and example were based on what I understood would be added to the ballot
draft, but which apparently never made it in. I recall discussing that
particular slide and example with Cliff to make sure I understood the
intent of the behavioral task force resolution of the enhancement. And I
still think I got the intent correct. In my opinion, The fact that a
vector net on the LHS of continuous assignment is _not_ inferred was an
editing error in the preparation of ballot draft. Unfortunately, the error
was not caught during the ballot, and is now part of the standard.
I raised a red flag on this issue with Cliff several months ago, when I was
going through "draft 6", the post-ballot LRM, to create the Verilog-2001
version of my quick reference guide. Cliff said he was sure it was in the
LRM somewhere, but didn't have time at that moment to look for it. I
finally decided to pull the enhancement from my reference guide, because I
could not find anywhere in the LRM that said a vector would be inferred on
the LHS of a continuous assignment.
So let me ask all of the BTF a question. Should I update the slide
presentation? I've left it alone, because changing it would mean it is no
longer the presentation I gave at HDLCon 2000. But, in addition to this
example on implicit nets for continuous assignments, there are some minor
errata in some of the examples. If companies really are considering my
slides as "a de facto LRM" instead of the IEEE 1364-2001 LRM, then perhaps
I should update the examples?
Stu
At 07:21 AM 8/1/2001, Paul Graham wrote:
>Precedence: bulk
>
>
>The following reply was made to PR errata/5; it has been noted by GNATS.
>
>From: Paul Graham <pgraham@cadence.com>
>To: Shalom.Bresticker@motorola.com
>Cc: btf-bugs@boyd.com
>Subject: Re: errata/5: Bad description of implicit nets created from
>continuous assignments
>Date: Wed, 1 Aug 2001 07:18:57 -0700 (PDT)
>
> > > Since the LRM has been through several drafts and has been approved
> by the
> > > IEEE with the existing wording, and since this new type of implicit
> > > declaration has some unresolved issues, I think that Verilog-2001 should
> > > omit this new feature.
> >
> > Which new feature ?
> > Since it's already in 6.1.2, it can't be omitted.
>
> The new feature that I meant is a declaration implied by an otherwise
> undefined assignment target. And it's not mentioned in 6.1.2. 6.1.2 only
> refers to implicit declarations, without defining them. And section 3.5,
> which defines then, doesn't mention the implicit declaration of an
> assignment target. The only written reference I have seen to this new
> feature is in Stuart Sutherland's nice overview of the Verilog-2000 features
> (slide 14) in which he gives this example:
>
> Verilog-2000 assign n = a * b; // defaults to wire, width of (a * b)
>
> which disagrees with your understanding that the implicit declaration
> should be a scalar.
>
> I wonder how many vendors have started implementation based on Sutherland's
> slides? They may well become the de-facto LRM. Why not -- they're much
> easier to read!
>
> Paul
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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