From: Michael McNamara (mac@verisity.com)
Date: Mon Sep 10 2001 - 16:09:08 PDT
Precedence: bulk
<p><p>Paul Graham writes:
> Precedence: bulk
>
> > I thought, wrongly, that both the wire type and vector size would be
> > inferred in a procedural assignment. In fact, the final wording of the
> > enhancement is very explicitly that only the wire data type is inferred.
>
> But this still leaves the question of whether an implicit net can be
> inferred from an assignment. Section 3.5 does not mention assignments as a
> source of implicit nets.
I agree. There is an oblique reference in section 6.1.2 that says
that continuous assigns and drive implicit nets, but it defers to
section 3.5 to define when this occurs; and 3.5 which clearly does not
allow continuous assigns to solely create nets. (at least as of draft
5).
>
> > The vector size can only inferred from a module port declaration, the same
> > as it was in Verilog-1995.
>
> I didn't know that the vector size could be inferred from the module port
> declaration. You mean that if x is not declared:
>
> some_module u1(.q(x), .d(blah));
> assign y = x[3];
>
> then x's range is determined by the size of some_module.q? Or am I
> misunderstanding this?
It would be inferred from the width of the input/output/inout
declaration, as in:
module foo (a);
output [31:7] a;
reg [31:0] b,c,d;
assign a = b&c|d;
endmodule
Notice that the line 'wire [31:7] a;' is missing? That is what Stuart
is talking about -- there is an implicit declaration of the wire that
goes along with a declaration of an input, output or input.
<p>This is described in section
>
> Paul
>
> --------------------
> Stefen Boyd Boyd Technology, Inc.
> stefen@BoydTechInc.com (408)739-BOYD
> www.BoydTechInc.com (408)739-1402 (fax)
>
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:46 PDT
and
sponsored by Boyd Technology, Inc.