Re: Verilog Standards Group - VOTE - (votes due Tuesday, October9, 2001)

From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Sun Oct 07 2001 - 00:16:04 PDT

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Cliff,

I approve the proposal.

Like Stu, I suggest you sell this to IEEE as fixing an error, not a clarification.

By the way, a still ambiguous case is the following:

assign a[0:3] = b ;

That is, the LHS of the continuous assignment is an undeclared variable which contains a range.

Shalom

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