| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 183
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| Category | enhancement
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| Synopsis | allow reverse part-select [lsb:msb]
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| State | open
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| Class | enhancement
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| Arrival-Date | Nov 05 2002
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| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
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| Release | 2001b
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| Environment |
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| Description |
--------------45E43DAD90A957E008739082 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Enhancement request: allow built-in bit-swapping eg., if I have a bus declared as qq[0:3], then I could refer to qq[3:0] in an expression and it would automatically expand it as {qq[3],qq[2],qq[1],qq[0]}. Is there anything like that in SystemVerilog? -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 "The devil is in the details." --------------45E43DAD90A957E008739082 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> Enhancement request: allow built-in bit-swapping
eg., if I have a bus declared as qq[0:3],
Is there anything like that in SystemVerilog?
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 "The devil is in the details." --------------45E43DAD90A957E008739082-- |
| Fix |
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| Audit-Trail |
From: Steven Sharp <sharp@cadence.com> To: etf-bugs@boyd.com Cc: Subject: Re: enhancement/183: allow reverse part-select [lsb:msb] Date: Wed, 6 Nov 2002 20:12:00 -0500 (EST) >Category: enhancement >Confidential: no >Originator: Steven Sharp <sharp@cadence.com> >Release: 2001b >Class: TBD >Description: >Enhancement request: > >allow built-in bit-swapping > >eg., if I have a bus declared as qq[0:3], >then I could refer to qq[3:0] in an expression >and it would automatically expand it as >{qq[3],qq[2],qq[1],qq[0]}. I think there are some serious problems with this. It is very easy to reverse the direction of a part select by accident. If it were legal, it would be very hard to find. It would also be easy to reverse the part selects both when writing and reading an object. This might cancel out and have no effect on the results and never get discovered, but drastically slow down simulation. Or someone might deliberately do it all over the place without realizing how expensive it is in simulation. And how often do you really need to reverse the significance of the bits in a vector? Bit-reverse addressing in DSPs for FFTs is the only reason I can think of off-hand. >Is there anything like that in SystemVerilog? No. Steven Sharp sharp@cadence.com |
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