| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 201
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| Category | enhancement
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| Synopsis | module instance without parentheses
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| State | open
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| Class | enhancement
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| Arrival-Date | Nov 19 2002
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| Originator | Shalom.Bresticker@motorola.com
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| Release | 2001b
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| Environment |
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| Description |
Following yesterday's ETF talk, is there any reason not to allow a module instance with no port connections not to have parentheses around an empty port list, but just a module name and a module instance name? |
| Fix |
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| Audit-Trail |
From: Peter Flake <Peter.Flake@synopsys.com> To: Shalom.Bresticker@motorola.com Cc: etf-bugs@boyd.com Subject: Re: enhancement/201: module instance without parentheses Date: Thu, 21 Nov 2002 11:30:50 +0000 >Category: enhancement >Confidential: no >Originator: Peter Flake <Peter.Flake@synopsys.com> >Release: 2001b >Class: TBD >Description: Hi Shalom, This proposal was in SystemVerilog and it has been deprecated by the Basic Committee, because it makes a module instance with no port declarations look like a variable declaration that has a user-defined type. These do not exist in Verilog, of course. Regards, Peter. At 02:03 PM 11/19/02 +0200, Shalom.Bresticker@motorola.com wrote: >Precedence: bulk > > > >Number: 201 > >Category: enhancement > >Originator: Shalom.Bresticker@motorola.com > >Environment: > >Description: > >Following yesterday's ETF talk, >is there any reason not to allow a module instance with no port >connections not >to have parentheses around an empty port list, but just a module name and a >module instance name? |
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