ISSUE 386

Add Proposal  Edit Analysis  Edit Class, Environment, or Release
Number 386
Category enhancement
Synopsis user defined functions on instantiations
State analyzed
Class enhancement
Arrival-DateJul 09 2003
Originator sharp@cadence.com
Release 2001b
Environment
Description
This is a request from my Verilog-AMS contact.

This appears to be a request to allow user-defined PLI
functions to be called in constant expressions. This
would raise some issues because there is no way of
knowing that the user-defined function is appropriate
for this use (effectively, a pure function). If it isn't,
this provides an easy way for the user to shoot themself
in the foot. It shouldn't be too difficult to implement.
Fix

Audit-Trail

Analyzed by etf@boyd.com on Wed Aug 6 07:15:39 2003
First, a correction to the proposal. What the AMS folks are actually calling for here is the ability to call user defined *HDL* functions in parameter overrides. For example, assume we have a Verilog function as follows:

function real f_mod(a, b)
input a; real a;
input b; real b;
begin
f_mod = (a-b*((a+0.5)/b)) ;
end
endfunction

Then what we want to be able to do is use this function to set the value of a parameter as follows:

parameter real aa= 10.0;
parameter real bb=3.0;
my_mod #(.r(a*f_mod(aa,bb)+b)) r1 (n1,n2);

The need for this arises from the need to specify more complex parameter expressions in analog netlists as represented in Verilog-AMS or Verilog.

It should be noted that this is very similar to what is currently allowed in VHDL-AMS in setting values of generics. This may or may not be a good reason to support it in Verilog as well.




From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 06 Aug 2003 17:19:44 +0300

Don't we already allow use of constant functions in parameter overrides?

Shalom


etf@boyd.com wrote:

> Precedence: bulk
>
> First, a correction to the proposal. What the AMS folks are actually calling for here is the ability to call user defined *HDL* functions in parameter overrides. For example, assume we have a Verilog function as follows:
>
> function real f_mod(a, b)
> input a; real a;
> input b; real b;
> begin
> f_mod = (a-b*((a+0.5)/b)) ;
> end
> endfunction
>
> Then what we want to be able to do is use this function to set the value of a parameter as follows:
>
> parameter real aa= 10.0;
> parameter real bb=3.0;
> my_mod #(.r(a*f_mod(aa,bb)+b)) r1 (n1,n2);
>
> The need for this arises from the need to specify more complex parameter expressions in analog netlists as represented in Verilog-AMS or Verilog.
>
> It should be noted that this is very similar to what is currently allowed in VHDL-AMS in setting values of generics. This may or may not be a good reason to support it in Verilog as well.
>
> http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=386

--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478




From: "Scott Cranston" <cranston@cadence.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 10:48:21 -0400

Only constant *expressions*. Function calls are not assumed to be
non-constant. I suppose we need a definition of a constant function
here, and then add this restriction to the original proposal.


From the LRM section on defparams:

------
The expression on the right-hand side of the defparam assignments shall
be a constant expression involving
only numbers and references to parameters.
------

There is no similar restriction mentioned in the instantion override
sections, but one would assume it is implied.


+++-----Original Message-----
+++From: Shalom Bresticker [mailto:Shalom.Bresticker@motorola.com]
+++Sent: Wednesday, August 06, 2003 10:30 AM
+++To: etf-bugs@boyd.com
+++Subject: Re: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++
+++
+++Precedence: bulk
+++
+++The following reply was made to PR enhancement/386; it has
+++been noted by GNATS.
+++
+++From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
+++To: etf-bugs@boyd.com
+++Cc:
+++Subject: Re: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++Date: Wed, 06 Aug 2003 17:19:44 +0300
+++
+++ Don't we already allow use of constant functions in
+++parameter overrides?
+++
+++ Shalom
+++
+++
+++ etf@boyd.com wrote:
+++
+++ > Precedence: bulk
+++ >
+++ > First, a correction to the proposal. What the AMS folks
+++are actually calling for here is the ability to call user
+++defined *HDL* functions in parameter overrides. For example,
+++assume we have a Verilog function as follows: > > function
+++real f_mod(a, b) > input a; real a; > input b; real b; > begin
+++ > f_mod = (a-b*((a+0.5)/b)) ;
+++ > end
+++ > endfunction
+++ >
+++ > Then what we want to be able to do is use this function
+++to set the value of a parameter as follows: >
+++ > parameter real aa= 10.0;
+++ > parameter real bb=3.0;
+++ > my_mod #(.r(a*f_mod(aa,bb)+b)) r1 (n1,n2);
+++ >
+++ > The need for this arises from the need to specify more
+++complex parameter expressions in analog netlists as
+++represented in Verilog-AMS or Verilog. > > It should be
+++noted that this is very similar to what is currently allowed
+++in VHDL-AMS in setting values of generics. This may or may
+++not be a good reason to support it in Verilog as well. > >
http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=386

--
Shalom Bresticker
Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9
9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9
9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50
441478




From: "Brad Pierce" <Brad.Pierce@synopsys.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 08:37:28 -0700

According to the third paragraph of V2K LRM Clause 4, constant expressions
can include constant function calls (as defined in V2K LRM 10.3.5).






From: "Scott Cranston" <cranston@cadence.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 11:46:11 -0400

I was unaware of this...guess it's already supported then.


+++-----Original Message-----
+++From: Brad Pierce [mailto:Brad.Pierce@synopsys.com]
+++Sent: Wednesday, August 06, 2003 11:40 AM
+++To: etf-bugs@boyd.com
+++Subject: RE: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++
+++
+++Precedence: bulk
+++
+++The following reply was made to PR enhancement/386; it has
+++been noted by GNATS.
+++
+++From: "Brad Pierce" <Brad.Pierce@synopsys.com>
+++To: <etf-bugs@boyd.com>
+++Cc:
+++Subject: RE: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++Date: Wed, 6 Aug 2003 08:37:28 -0700
+++
+++ According to the third paragraph of V2K LRM Clause 4,
+++constant expressions can include constant function calls
+++(as defined in V2K LRM 10.3.5).
+++
+++
+++
+++
+++
+++

From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 12:12:24 -0400 (EDT)

It certainly sounds like they are asking for constant functions as added
to Verilog-2001. These are documented in 10.3.5. That section mostly
deals with restrictions on the functions themselves, and doesn't say much
about where they can be used. I don't know if there is text elsewhere
that clarifies that. I believe that the intent was that they could be
used in any constant expression.

Steven Sharp
sharp@cadence.com


From: Michael McNamara <mac@verisity.com>
To: Steven Sharp <sharp@cadence.com>
Cc: etf-bugs@boyd.com
Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 10:58:26 -0700

Steven Sharp writes:
> Precedence: bulk
>
> The following reply was made to PR enhancement/386; it has been noted by GNATS.
>
> From: Steven Sharp <sharp@cadence.com>
> To: etf-bugs@boyd.com
> Cc:
> Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
> Date: Wed, 6 Aug 2003 12:12:24 -0400 (EDT)
>
> It certainly sounds like they are asking for constant functions as added
> to Verilog-2001. These are documented in 10.3.5. That section mostly
> deals with restrictions on the functions themselves, and doesn't say much
> about where they can be used. I don't know if there is text elsewhere
> that clarifies that. I believe that the intent was that they could be
> used in any constant expression.
>
> Steven Sharp
> sharp@cadence.com
>

Constant functions were created specifically to enable compile time
control of hierarchy based on parameterized module definition.

For example, one might need a log(n) number of cells to implement a n
sized multiplier cell; and rather than defining a log built in
function, and then having users wanting also sqrt, or whatever; we
instead defined the ability for users to create constant functions
that do whatever the design team wants, if they follow rules that
insure these can be called at compile time.

-mac


From: Shalom.Bresticker@motorola.com
To: etf-bugs@boyd.com
Cc:
Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Mon, 11 Aug 2003 12:40:49 +0300 (IDT)

In addition to what Brad pointed out, that section 4, paragraph 3, states
that constant function calls can appear in constant expressions,
note that in the BNF, "constant_function_call" is one of the options for
"constant_primary", "module_path_primary", and for "primary". See A.8.4.

By the way, "module_path_primary" and "primary" include as options
"function_call", "system_function_call", and "constant_function_call".
At first glance, it would appear that "function_call" would be sufficient,
and the other two are included in it.

> It certainly sounds like they are asking for constant functions as added
> to Verilog-2001. These are documented in 10.3.5. That section mostly
> deals with restrictions on the functions themselves, and doesn't say much
> about where they can be used. I don't know if there is text elsewhere
> that clarifies that. I believe that the intent was that they could be
> used in any constant expression.

Shalom


From: Steven Sharp <sharp@cadence.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Mon, 11 Aug 2003 15:21:05 -0400 (EDT)

We now have indications that they were asking for user-defined system functions
after all, not Verilog functions.

Steven Sharp
sharp@cadence.com

Unformatted



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