ISSUE 388

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Number 388
Category enhancement
Synopsis genvar in behavior
State open
Class enhancement
Arrival-DateJul 09 2003
Originator sharp@cadence.com
Release 2001b
Environment

Description
This is a request from my Verilog-AMS contact.

They asked for some way of using generate loops within
behavioral code. I don't believe that there is any reason
to do this. In most cases, replicating a series of
procedural statements in a sequential block by putting
them inside a generate loop would be equivalent to
putting the same statements inside an ordinary for-loop.
Either way the statements would execute repeatedly; it
would just be an unrolled loop in the generate case.

I think that this request came because they have defined
some constructs in AMS that are neither procedural
statements (which could be put into an ordinary for-loop)
or concurrent statements/processes/declarations (which
could be put into a generate for-loop). Everything in
digital Verilog falls into one of these two categories
and is therefore already handled. They should probably
fix AMS so that their analog constructs fall cleanly into
one of these two categories also.

I am entering this as a placeholder, just for completeness.
I oppose actually adding such a thing.
Fix

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