| Add Proposal | Add Analysis | Edit Class, Environment, or Release |
| Number | 521
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| Category | errata
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| Synopsis | section 7: connection of vector to gate terminal
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| State | open
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| Class | errata-discuss
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| Arrival-Date | Dec 28 2003
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| Originator | Shalom Bresticker <Shalom.Bresticker@motorola.com>
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| Release | 2001b
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| Description |
What happens when you connect a vector to a gate terminal ? The LRM does not say. In the case of an input terminal, I can think of (at least) three interpretations. 1. Use the least significant bit. (This seems to be what VCS does.) 2. Relate to it as 1 if non-zero, 0 if zero. (This seems to be what VXL and NCV do.) 3. Expand the primitive to use all the bits, i.e., interpret and (out, in1, in2[1:0]) as and (out, in1, in2[1], in2[0]) Use of a vector for an inout or output terminal is also ambiguous. -- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478 |
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