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| Number | 529
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| Notify-List |
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| Category | enhancement
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| Synopsis | Add "bidirectional skew" timing check
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| State | open
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| Class | enhancement
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| Arrival-Date | Jan 20 2004
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| Originator | Shalom.Bresticker@motorola.com
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| Description |
The SDF standard includes a TIMINGCHECK construct called BIDIRECTSKEW, which is not mentioned in the 1364 standard. Ted Elkind wrote: Bidirectskew was intended to anticipate a potential enhancement to 1364. I should probably say a little more about bidirectskew. It was intended to address the situation where two signals have skew relative to one another, and either one could occur first. The only way the Verilog language can address this situation at present is with 2 $skew checks (apologies if the syntax is wrong, it's been a while): $skew(posedge clka, posedge clkb, 6); $skew(posedge clkb, posedge clka, 6); Even without bidirectskew being part of 1364, the SDF bidirectskew can still be used to annotate to $skew. For example (again, apologies for syntax): (bidirectskew (posege clka) (posedge clkb) (6, 7)) This would annotate 6 to the first $skew and 7 to the second $skew. |
| Fix |
Unknown |
| Unformatted |
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