reg        [5:0] a;  
    reg signed [4:0] b;
 
    initial begin
      a = 8'hff; // After the assignment, a = 6'h3f
      b = 8'hff; // After the assignment, b = 5'h1f
    end
 
 Example:
    reg        [0:5] a;  
    reg signed [0:4] b, c;  

    initial begin
      a = 8'sh8f; // After the assignment, a = 6'h0f
      b = 8'sh8f; // After the assignment, b = 5'h0f
      c = -113;   // After the assignment, c = 15
    end
    // 1000_1111 = (-'h71 = -113) truncates to ('h0F = 15)
 
 Example:
    reg        [7:0] a;
    reg signed [7:0] b;  
    reg signed [5:0] c, d;

    initial begin
      a = 8'hff;
      c = a;      // After the assignment, c = 6'h3f
      b = -113;
      d = b;      // After the assignment, d = 6'h0f
    end

module dimm (adr, ba, rasx, casx, csx, wex, dqm, cke, data, clk,
dev_id);
  parameter [31:0] MEM_SIZE  = 8,  // in mbytes
                   MEM_WIDTH = 16;
  input [10:0] adr;
  input        ba;
  input        rasx, casx, csx, wex;
  input [ 7:0] dqm;
  input        cke;
  inout [63:0] data;
  input        clk;
  input [ 4:0] dev_id;

  genvar       i;

  generate
    case ({MEM_SIZE, MEM_WIDTH})
      {32'd8, 32'd16}: // 8Meg x 16 bits wide.
      begin
        // The generated instance names are word[3].p, word[2].p,
        // word[1].p, word[0].p, and the task read_mem
        for (i=0; i<4; i=i+1) begin:word
          sms_16b216t0 p (.clk(clk), .csb(csx), .cke(cke),
              .ba(ba[0]), .addr(adr[10:0]), .rasb(rasx), 
              .casb(casx), .web(wex), .udqm(dqm[2*i+1]), 
              .ldqm(dqm[2*i]), .dqi(data[15+16*i:16*i]), 
              .dev_id(dev_id[4:0]));
        end
        task read_mem;
          input  [31:0] address;
          output [63:0] data;
          begin
            word[3].p.read_mem(address, data[63:48]);
            word[2].p.read_mem(address, data[47:32]);
            word[1].p.read_mem(address, data[31:16]);
            word[0].p.read_mem(address, data[15:0]);
          end
        endtask
      end
      
      {32'd16, 32'd8}: // 16Meg x 8 bits wide.
        begin
          // The generated instance names are byte[7].p,
	  byte[6].p,
          // byte[5].p, byte[4].p, byte[3].p, byte[2].p,
	  byte[1].p,
          // byte[0].p and the task read_mem
          for (i=0; i<8; i=i+1) begin:byte
            sms_16b208t0 p (.clk(clk), .csb(csx), .cke(cke),
                .ba(ba[0]), .addr(adr[10:0]), .rasb(rasx), 
                .casb(casx), .web(wex), .dqm(dqm[i]), 
                .dqi(data[7+8*i:8*i]),.dev_id(dev_id[4:0]));
          end
          task read_mem;
            input  [31:0] address;
            output [63:0] data;
            begin
              byte[7].p.read_mem(address, data[63:56]);
              byte[6].p.read_mem(address, data[55:48]);
              byte[5].p.read_mem(address, data[47:40]);
              byte[4].p.read_mem(address, data[39:32]);
              byte[3].p.read_mem(address, data[31:24]);
              byte[2].p.read_mem(address, data[23:16]);
              byte[1].p.read_mem(address, data[15:8]);
              byte[0].p.read_mem(address, data[7:0]);
            end
          endtask
        end
      // Other memory cases ...
    endcase
  endgenerate
endmodule

module tb1;

  wire [9:0] out_a, out_d;
  wire [4:0] out_b, out_c;
  reg  [9:0] in_a, in_d;
  reg  [4:0] in_b, in_c;
  reg        clk;

  // testbench clock & stimulus generation code ...
  
  // Four instances of vdff with parameter value assignment by ordered list

  // mod_a has new parameter values size=10 and delay=15
  // mod_b has default parameters (size=5, delay=1)
  // mod_c has one default size=5 and one new delay=12
  //   Note that in order to change the value of delay,
  //   it is necessary to specify the (default) value of size as well.
  // mod_d has a new parameter value size=10. delay retains its default value

  vdff #(10,15) mod_a (.out(out_a), .in(in_a), .clk(clk));
  vdff          mod_b (.out(out_b), .in(in_b), .clk(clk));
  vdff #( 5,12) mod_c (.out(out_c), .in(in_c), .clk(clk));
  vdff #(10)    mod_d (.out(out_d), .in(in_d), .clk(clk));

endmodule

module vdff (out, in, clk);
  parameter size=5, delay=1;
  output [size-1:0] out;
  input  [size-1:0] in;
  input             clk;
  reg    [size-1:0] out;
  
  always @(posedge clk)
    #delay out = in;

endmodule

module tb2;

  wire [9:0] out_a, out_d;
  wire [4:0] out_b, out_c;
  reg  [9:0] in_a, in_d;
  reg  [4:0] in_b, in_c;
  reg        clk;

  // testbench clock & stimulus generation code ...
  
  // Four instances of vdff with parameter value assignment by name

  // mod_a has new parameter values size=10 and delay=15
  // mod_b has default parameters (size=5, delay=1)
  // mod_c has one default size=5 and one new delay=12
  // mod_d has a new parameter value size=10. delay retains its default value

  vdff #(.size(10),.delay(15)) mod_a (.out(out_a), .in(in_a), .clk(clk));
  vdff                         mod_b (.out(out_b), .in(in_b), .clk(clk));
  vdff #(.delay(12))           mod_c (.out(out_c), .in(in_c), .clk(clk));
  vdff #(.delay( ), .size(10)) mod_d (.out(out_d), .in(in_d), .clk(clk));

endmodule


module vdff #(parameter size=5, delay=1)
  (output reg [size-1:0] out,
   input      [size-1:0] in,
   input                 clk);

  always @(posedge clk)
    #delay out = in;

endmodule

module tb3;
  // declarations & code ...

  // legal mixture of instance with positional parameters and 
  // another instance with named parameters

  vdff #(10, 15)     mod_a (.out(out_a), .in(in_a), .clk(clk));
  vdff               mod_b (.out(out_b), .in(in_b), .clk(clk));
  vdff #(.delay(12)) mod_c (.out(out_c), .in(in_c), .clk(clk));

endmodule

  // mod_a instance with ILLEGAL mixture of parameter assignments
  vdff #(10, .delay(15)) mod_a (.out(out_a), .in(in_a), .clk(clk));

 
     block_item_declaration ::=
         { attribute_instance } block_reg_declaration
       | { attribute_instance } event_declaration
       | { attribute_instance } integer_declaration
       | { attribute_instance } local_parameter_declaration
       | { attribute_instance } parameter_declaration
       | { attribute_instance } real_declaration
       | { attribute_instance } realtime_declaration
       | { attribute_instance } time_declaration
 
     block_reg_declaration ::=
         "reg" [ "signed" ] [ range ] list_of_block_variable_identifiers ";"
 
     list_of_block_variable_identifiers ::=
         block_variable_type { "," block_variable_type }
 
     block_variable_type ::=
         variable_identifier
       | variable_identifier dimension { dimension }

block_item_declaration ::=
    {attribute_instance} "reg" ["signed"] [range] list_of_block_variable_identifiers ";"
  | {attribute_instance} "integer"  list_of_block_variable_identifiers ";"
  | {attribute_instance} "time"     list_of_block_variable_identifiers ";"
  | {attribute_instance} "real"     list_of_block_real_identifiers ";"
  | {attribute_instance} "realtime" list_of_block_real_identifiers ";"
  | {attribute_instance} event_declaration
  | {attribute_instance} local_parameter_declaration
  | {attribute_instance} parameter_declaration

list_of_block_variable_identifiers ::=
    block_variable_type { "," block_variable_type }
  
list_of_block_real_identifiers ::=
    block_real_type     { "," block_real_type }
  
block_variable_type ::= variable_identifier { dimension }
block_real_type ::=     real_identifier     { dimension }

c = {a**b};              // expression a**b is self determined
$display ("a**b=%x", c); // due to {}

c = {a**b}; // expression a**b is self determined
            // due to concatenation operator {}
$display ("a**b=%x", c); 

$display ("a*b=%x", a*b); // expression size is self determined
c = {a**b};               // expression a**b is self determined
$display ("a**b=%x", c);  // due to {}
c = a**b;                 // expression size is determined by c
$display ("c=%x", c);

$display ("a*b=%h", a*b); // expression size is self determined
c = {a**b};               // expression a**b is self determined
                          // due to concatenation operator {}
$display ("a**b=%h", c); 
c = a**b;                 // expression size is determined by c
$display ("c=%h", c);

static double
chi_square(seed,deg_of_free)
long *seed,deg_of_free;
{
    double x;
    long k;
    if(deg_of_free % 2)
    {
        x = normal(seed,0,1);
        x = x * x;
    }
    else
    {
        x = 0.0;
    }
    for(k = 2;k <= deg_of_free;k = k + 2)
    {
        x = x + 2 * exponential(seed,1);
    }
    return(x);
}

+-----------------------------+------------+--------------------------+
| Expression                  | Bit Length | Comments                 |
+-----------------------------+------------+--------------------------+
| i op j, where op is         |   1        | operands are sized to    |
|   === !== == != > >= < <=   |            | max(L(i), L(j)           |
+-----------------------------+------------+--------------------------+
| i op j, where op is         |   1        | All operands are         |
|   && ||                     |            | self-determined          |
+-----------------------------+------------+--------------------------+

{4{w}} // This is equivalent to {w, w, w, w} 

{   0{1'b0}}  //illegal 
{1'bz{1'b0}}  //illegal 
{1'bx{1'b0}}  //illegal 

   procedural_timing_control_statement ::=
         delay_or_event_control   statement_or_null

   procedural_timing_control_statement ::=
         procedural_timing_control   statement_or_null

`define STRING reg [1024 * 8:1]

module goodtasks;
  `STRING str;
  integer int;
  reg [31:0] vect;
  real realvar;

  initial
    begin
      if ($value$plusargs("TEST=%d",int))
        $display("value was %d",int);
      else
        $display("+TEST= not found");
      #100 $finish;
    end

endmodule

module ieee1364_example;
  real frequency;
  reg [8*32:1] testname;
  reg [64*8:1] pstring;
  reg clk;

  initial
    begin
      if ($value$plusargs("TESTNAME=%s",testname))
        begin
          $display(" TESTNAME= %s.",testname);
          $finish;
        end

      if (!($value$plusargs("FREQ+%0F",frequency)))
        frequency = 8.33333; // 166 MHz
      $display("frequency = %f",frequency);

      pstring = "TEST%d";
      if ($value$plusargs(pstring, testname))
        $display("Running test number %0d.",testname);
    end

endmodule

+TEST=5 

value was           5
frequency = 8.333330
Running text number x.

+TESTNAME=bar

+TEST= not found
 TESTNAME=                              bar.

+FREQ+9.234

+TEST= not found
frequency = 9.234000

+TEST23

+TEST= not found
frequency = 8.333330
Running test number 23.

| { attribute_instance } local_parameter_declaration
| { attribute_instance } parameter_declaration

| { attribute_instance } local_parameter_declaration ";"
| { attribute_instance } parameter_declaration ";"

local_parameter_declaration ::=  
    localparam [ signed ] [ range ] list_of_param_assignments ;
  | localparam integer  list_of_param_assignments ;
  | localparam real     list_of_param_assignments ;
  | localparam realtime list_of_param_assignments ;
  | localparam time     list_of_param_assignments ;

parameter_declaration ::=
    parameter [ signed ] [ range ] list_of_param_assignments ;
  | parameter integer   list_of_param_assignments ;
  | parameter real      list_of_param_assignments ;
  | parameter realtime  list_of_param_assignments ;
  | parameter time      list_of_param_assignments ;

local_parameter_declaration ::=  
    localparam [ signed ] [ range ] list_of_param_assignments
  | localparam integer  list_of_param_assignments 
  | localparam real     list_of_param_assignments 
  | localparam realtime list_of_param_assignments 
  | localparam time     list_of_param_assignments 

parameter_declaration ::=
    parameter [ signed ] [ range ] list_of_param_assignments
  | parameter integer   list_of_param_assignments 
  | parameter real      list_of_param_assignments 
  | parameter realtime  list_of_param_assignments 
  | parameter time      list_of_param_assignments 

1. In 2.5.1:

A. CHANGE the third sentence of paragraph 2 FROM

"The second form specifies a size constant, which shall be 
composed of up to three tokens-an optional size constant, a 
single quote followed by a base format character, and the 
digits representing the value of the number."

TO:

"The second form specifies a based constant, which shall be 
composed of up to three tokens-an optional size constant, an
apostrophe character (', ASCII 0x27) followed by a base 
format character, and the 
digits representing the value of the number."

(Note that issue #267 changes "size constant" to "based 
constant".)

B. CHANGE the first sentence of paragraph 5 FROM

"The second token, a base_format, shall consist of a 
case-insensitive letter specifying the base for the number, 
optionally preceded by the single character s (or S) to 
indicate a signed quantity, preceded by the single quote 
character (')."

TO:

"The second token, a base_format, shall consist of a 
case-insensitive letter specifying the base for the number, 
optionally preceded by the single character s (or S) to 
indicate a signed quantity, preceded by the apostrophe
character."

C. CHANGE paragraph 7 FROM

"The single quote and the base format character shall not 
be separated by any white space."
 
TO:

"The apostrophe character and the base format character 
shall not be separated by any white space."


2. CHANGE the first sentence of 2.7.5 FROM

"The ` character (the ASCII value 60, called open quote 
or accent grave) introduces a language construct used to 
implement compiler directives."

TO:

"The ` character (the ASCII value 0x60, called 
grave accent) introduces a language construct used to 
implement compiler directives."


3. CHANGE the first three sentences of section 19 FROM

"All Verilog compiler directives are preceded by the (` ) 
character. This character is called accent grave. It is 
different from the character ('), which is the single quote 
character."

TO

"All Verilog compiler directives are preceded by the (` ) 
character. This character is called grave accent
(ASCII 0x60). It is 
different from the character ('), which is the apostrophe
character (ASCII 0x27)."

(Note to editor:
The ` and ' characters should be in Courier font.
The apostrophe character should be straight vertical, not
slanted.)


4. The term "single quote" appears in 25.52-53, 55-56 in the
phrase "A character in single quotes ...", referring to C code.
Leave the phrase as is in those places.


5. Editor to make sure that everywhere the apostrophe character
is supposed to appear in code text, both Verilog and C, the 
plain straight up-and-down apostrophe character is used, not a 
curly quote nor a slanted quote character.

Similarly, make sure that the regular plain grave accent 
character is used wherever it is needed, not a curly version.

Similarly, double quotes in code text should be regular 
straight up-and-down quotation marks, not 'smart', slanted
quotes.

(Note to editor: change CourierNew font to Courier, 
 TimesNewRoman to Times.) 

 
  
The following fix incorporates and supercedes issue #181. 
 
In "primary" BNF in Syntax 4-2 and in A.8.4, 
CHANGE the following 4 lines from: 
 
| hierarchical_identifier 
| hierarchical_identifier [ expression ] { [ expression ] } 
| hierarchical_identifier [ expression ] { [ expression ] } [ range_expression ] 
| hierarchical_identifier [ range_expression ] 
 
TO: 
 
| hierarchical_identifier [ {"["expression"]"} "["range_expression"]" ] 
 
 
The following fix partly supercedes issue #53. 
 
In "net_lvalue" BNF in Syntax 9-3 and in A.8.5, 
CHANGE the following 4 lines from: 
 
| hierarchical_net_identifier 
| hierarchical_net_identifier [ constant_expression ] { [ constant_expression ] } 
| hierarchical_net_identifier [ constant_expression ] { [ constant_expression ] }[ constant_range_expression ] 
| hierarchical_net_identifier [ constant_range_expression ] 
 
TO: 
 
| hierarchical_net_identifier [ {"["constant_expression"]"} 
"["constant_range_expression"]" ] 
 
 
The following fix partly supercedes #53. 
 
In "variable_lvalue" BNF in Syntaxes 9-1, 9-2, 9-3, and in
A.8.5, 
CHANGE the following 4 lines from: 
 
| hierarchical_variable_identifier 
| hierarchical_variable_identifier [ expression ] { [ expression ] } 
| hierarchical_variable_identifier [ expression ] { [ expression ] }[ range_expression ] 
| hierarchical_variable_identifier [ range_expression ] 
 
TO: 
 
| hierarchical_variable_identifier [ {"["expression"]"} "["range_expression"]" ] 
 

localparam adder_width = clogb2(ram_depth);
input [adder_width-1:0] address ;

localparam addr_width = clogb2(ram_depth);
input [addr_width-1:0] address ;

function integer clogb2 ;
input depth ;
integer i, result ;
begin
  for (i=0; 2**i < depth; i=i+1)
    result = i + 1 ;
  clogb2 = result ;
end
endfunction

  function integer clogb2 ;
    input [31:0] value ;
    begin
      value = value - 1 ;
      for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) 
        value = value >> 1 ;
    end
  endfunction

library_declaration ::= 
library library_identifier file_path_spec [ { , file_path_spec } ]
    [ -incdir file_path_spec [ { , file_path_spec } ] ;  

TO:

library_declaration ::= 
library library_identifier file_path_spec { , file_path_spec }
    [ -incdir file_path_spec { , file_path_spec } ] ;  

liblist_clause ::= liblist [{library_identifier}]  

TO:

liblist_clause ::= liblist { library_identifier }

escaped_hierarchical_identifier ::= (From Annex A - A.9.3)
  escaped_hierarchical_branch 
    [ { .simple_hierarchical_branch | .escaped_hierarchical_branch } ]

TO:

escaped_hierarchical_identifier ::= (From Annex A - A.9.3)
  escaped_hierarchical_branch 
    { .simple_hierarchical_branch | .escaped_hierarchical_branch }

simple_hierarchical_branch ::=  
          simple_identifier [ [ unsigned_number ] ]  
                [ { .simple_identifier [ [ unsigned_number ] ] } ]  

escaped_hierarchical_branch ::=  
          escaped_identifier [ [ unsigned_number ] ]  
                [ { .escaped_identifier [ [ unsigned_number ] ] } ]  

TO:

simple_hierarchical_branch ::=  
          simple_identifier  [ [ unsigned_number ] ]  
                { .simple_identifier  [ [ unsigned_number ] ] }

escaped_hierarchical_branch ::=  
          escaped_identifier [ [ unsigned_number ] ]  
                { .escaped_identifier [ [ unsigned_number ] ] }

                op1 is    negative<-1     -1                 zero     1    positive>1
              ------------------------------------------------------------------------
              op2 is            
              positive    op1 ** op2   op2 is odd -> -1       0       1    op1 ** op2
                                       op2 is even -> 1
            
              zero           1             1                  1       1       1
            
              negative       0         op2 is odd -> -1      'bx      1       0
                                       op2 is even -> 1

              Expression         Result       Comments
              3**2               9            3*3
              2**3               8            2*2*2
              2**0               1            anything to the zero exponent is 1
              0**0               1            zero to the zero exponent is also 1
              2.0**-3'sb1        0.5          2.0 is real, giving real reciprocal     
              2**-3'sb1          0            2**-1 = 1/2 Integer division truncates to zero
              0**-1              'bx          0**-1 = 1/0 Integer division by zero is 'bx
              9**0.5             3.0          Real square root
              9.0**(1/2)         1.0          Integer division truncates exponent to zero
              -3.0**2.0          9.0          Defined, because real 2.0 is still integral value

"Although the names of compiler directives are contained in the same
name space as text macro names, the names of compiler directives are considered
not to be defined by `ifdef, `ifndef, and `elsif."

FIX:
Remove first copy of paragraph.

REPLACE occurances of "ifdef", "ifndef",
"elsif", and "else" in fixed-font (without
back-tic) in 19.4, in paragraphs beginning with "The `ifdef,
`else, `elsif, and `endif compiler directives work together in
the following manner:"

WITH:
"`ifdef", "`ifndef", "`elsif", and
"`else" in Bold Times font (with back-tic).

In section 12.1.3.2 example 5: 

Change the for loop condition  on the first line after the 
generate <bold generate> from:

 (i=0; i<SIZE+1; i=i+1) to:
 (i=0; i<SIZE; i=i+1)  

On the next line in the comment change:

B1[i].N1[i]  to:
B1[i].N1   

list_of_event_identifiers ::= 
  event_identifier [ dimension { dimension }] 
    { , event_identifier [ dimension { dimension }] } 

list_of_event_identifiers ::= 
  event_identifier { dimension }
    { , event_identifier { dimension } } 

list_of_net_identifiers ::= 
  net_identifier [ dimension { dimension }] 
    { , net_identifier [ dimension { dimension }] } 

list_of_net_identifiers ::= 
  net_identifier { dimension }
    { , net_identifier { dimension } }

reg [31: 0] big_vect;
reg [0 :31] little_vect;
reg [63: 0] dword;
integer sel;

big_vect[ 0 +: 8]    // == big_vect[ 7 : 0]
big_vect[15 -: 8]    // == big_vect[15 : 8]

little_vect[ 0 +: 8] // == little_vect[0 : 7]
little_vect[15 -: 8] // == little_vect[8 :15]

dword[8*sel +: 8]    // variable part-select with fixed width

REPLACE:

port_reference ::= (A.1.4, Syntax 12-1, 12-5)
  port_identifier 
| port_identifier [ constant_expression ] 
| port_identifier [ range_expression ] 

specify_input_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  input_identifier 
| input_identifier [ constant_expression ] 
| input_identifier [ range_expression ]  

specify_output_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  output_identifier 
| output_identifier [ constant_expression ] 
| output_identifier [ range_expression ]  

WITH:
              
port_reference ::= (A.1.4, Syntax 12-1, 12-5)
  port_identifier [ [ constant_range_expression ] ] 

specify_input_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  input_identifier [ [ constant_range_expression ] ] 

specify_output_terminal_descriptor ::= (A.7.3, Syntax 14-3)
  output_identifier [ [ constant_range_expression ] ] 

              The first column should look like this:

              file top.v
              module top();
              adder a1 (...) ;
              adder a2 (...) ;
              endmodule

              The second column should look like this:

              file adder.v
              module adder(...);
              //rtl adder description
              ...
              endmodule

              The third column should look like this:

              file adder.vg
              module adder(...);
              //gate-level adder description
              ...
              endmodule

`ifndef last_result
   initial $display("first_block, second_block, last_result
              not defined.");
`elsif real_last
   initial $display("first_block, second_block not defined,
              last_result and real_last defined.");

CHANGE

parallel_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] specify_input_terminal_descriptor "=>" 
        specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")" 

TO 

parallel_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] specify_input_terminal_descriptor "=>" 
        "(" specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")" ")" 

and

CHANGE

full_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] list_of_path_inputs "*>" 
        list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" 

TO

full_edge_sensitive_path_description ::= 
        "(" [ edge_identifier ] list_of_path_inputs "*>" 
        "(" list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")" 

              " include_statement = include < file_path_spec > ; "

              TO 

              " include_statement = include file_path_spec ; "